1. Field of the Invitation
The present invention relates to a method for manufacturing a semiconductor device having a bipolar transistor and a polycrystalline silicon resistor on the same semiconductor substrate.
2. Description of the Related Art
In a semiconductor device having an active element such as a bipolar transistor and a passive element such as a resistor, in order to improve the performance of the device, i.e., in order to enhance the operation speed and the operation frequency, it is essential to reduce the parasitic capacitance of the resistor, in addition to the improvement of the performance of the bipolar transistor.
An impurity-doped polycrystalline silicon resistor which can be formed on a thick insulating layer has a smaller parasitic capacitance as compared with an impurity diffusion layer resistor.
In a prior art method for manufacturing an NPN-type bipolar transistor and a phosphorus-doped polycrystalline silicon resistor, an N+-type buried layer is formed within a P-type semiconductor substrate, and then, an N-type epitaxial layer collector region is formed thereon. Then, a P-type impurity diffusion layer base region is formed within the N-type epitaxial layer. After that, an insulating layer is formed on the entire surface. Then, a non-doped polycrystalline silicon layer is deposited by a chemical vapor deposition (CVD) process, and phosphorus ions are doped thereinto by an ion implantation process. The phosphorus-doped polycrystalline silicon layer is annealled and patterned, to thereby form a phosphorus-doped polycrystalline silicon resistor. Finally, an N-type impurity diffusion layer emitter region is formed within the P-type impurity diffusion layer (base region). This will be explained later in detail.
The reason why the phosphorus-doped polycrystalline silicon layer is annealled or heated is as follows:
i) If phosphorus ions are doped by an ion implantation method or the like into the polycrystalline silicon layer, the concentration distribution of phosphorus in the polycrystalline silicon along its perpendicular direction is not uniform. Therefore, if the phosphorus-doped polycrystalline silicon layer is etched without performing an annealling or heating process thereupon, the etched phosphorus-doped polycrystalline silicon layer is so overhung that other connections are shorted or disconnected. In order to avoid this, the phosphorus-doped polycrystalline silicon layer is annealled at a relatively low temperature, such as 800.degree. C., before the etching operation thereof (see: JP-A-63-65664).
ii) If a silicon nitride layer formed by a plasma CVD process is formed on the polycrystalline silicon layer, unsaturated bonds of silicon included in the polycrystalline silicon layer are passivated by hydrogen included in the silicon nitride layer. As a result, the resistance of the polycrystalline silicon resistor fluctuates. In order to avoid this, an annealling operation at a relatively low temperature is carried out to diffuse hydrogen from the silicon nitride layer to the polycrystalline silicon layer, to saturate the unsaturated bonds of silicon thereof with hydrogen. Thus, the resistance of the polycrystalline silicon layer can be stabilized (see: JP-A-64-42851).
iii) If a silicon nitride layer is formed directly on the polycrystalline silicon layer, a large stress is applied to the silicon nitride layer. In order to avoid this, a light thermal oxidization is performed upon the polycrystalline silicon layer before the deposition of the silicon nitride layer, so that the stress upon the polycrystalline silicon layer can be relaxed by a thin silicon oxide layer therebetween (see: JP-A-57-128054).
In the above-mentioned prior art manufacturing method, however, since the annealling or heating operation performed upon the impurity-doped polycrystalline silicon layer is carried out after the formation of the base region, this annealling or heating operation is insufficient in view of the effect of the concentration distribution of impurities of the polycrystalline silicon layer. As a result, the resistance of the impurity-doped polycrystalline silicon resistor is not stable, since latter steps such as an emitter forming step and a plasma passivation layer forming step also affect the resistance of the impurity-doped polycrystalline silicon resistor.
On the other hand, in a bipolar high integrated circuit, in order to enhance the operation speed, the base region is made thinner. Therefore, even a low temperature annealling or heating operation performed upon the impurity-doped polycrystalline silicon layer affects the shape and concentration distribution of the base region, thus deteriorating the performance of the bipolar transistor.